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FEDL9090A-01
1 Semiconductor ML9090A-01, -02
LCD Driver with Key Scanner and RAM
This version:
May 2001
GENERAL DESCRIPTION
The ML9090A-01 and ML9090A-02 are LCD drivers that contain internal RAM and a key scan function. They are best suited for car audio displays. Since 1-bit data of the display data RAM corresponds to the light-on or light-off of 1-dot of the LCD panel (a bit map system), a flexible display is possible. A single chip can implement a graphic display system of a maximum of 80 x 18 dots (80 x 10 dots for the ML9090A-01, 80 x 18 dots for the ML9090A-02). Since containing voltage multipliers, the ML9090A-01 and ML9090A-02 require no power supply circuit to drive the LCD. Since the internal 5 x 5 scan circuit has eliminated the needs of key scanning by the CPU, the ports of the CPU can be efficiently used.
FEATURES
Logic voltage: 2.7 to 5.5 V LCD drive voltage: 6 to 16 V (positive voltage) 80 segment outputs, 10 common outputs for ML9090A-01 and 18 common outputs for ML9090A-02 Built-in bit-mapped RAM (ML9090A-01: 80 x 10 = 800 bits, ML9090A-02: 80 x 18 = 1440 bits) 4-pin serial interface with CPU: CS, CP, DI/O, KREQ Built-in LCD drive bias resistors Built-in voltage doubler or tripler circuit Built-in 5 x 5 key scanner Port A output : 1 pin, output current: -15 mA: (may be used for LED driving) Port B output : 8 pins Output current (available for the ML9090A-01 only) -2 mA : 5 pins -15 mA : 3 pins * Temperature range: -40 to +85C * Package: 128-pin plastic QFP (QFP128-P-1420-0.50-K) (Product name: ML9090A-01GA) (Product name: ML9090A-02GA) Comparison between the ML9090A-01 and the ML9090A-02
Item Number of common outputs Number of dots on the LCD screen (selectable by program) Number of port A outputs Number of port B outputs ML9090A-01 10 Max. 8 x 80 9 x 80 10 x 80 1 8 ML9090A-02 18 Max. 16 x 80 17 x 80 18 x 80 1 --
* * * * * * * * * *
1/41
FEDL9090A-01
1 Semiconductor
ML9090A-01, -02
BLOCK DIAGRAM (1/2)
ML9090A-01
COM1 VIN VC1 VC2 VS1 VS2 DT
VOLTAGE DOUBLER/ TRIPLER
COM10 PB0
PB7 SEG1
SEG80
10-OUT COMMON DRIVER
8-PORT 80-OUT SEGMENT DRIVER DRIVER
SHIFT REGISTER
DATA LATCH
V2 V3B
LCD BIAS
LINE ADDRESS DECODER
Y ADDRESS COUNTER
Y ADDRESS DECODER
VOLTAGE DIVIDING
V3A
CIRCUIT
DISPLAY DATA RAM 80 x 10 BITS
INPUT OUTPUT INTERFACE
CP DI/O
CONTROL REGISTER
CS
I/O BUFFER
X ADDRESS DECODER
X ADDRESS COUNTER
TIMING GENERATOR
X ADDRESS REGISTER
OSC1 OSC2
OSCILLATION CIRCUIT
1 PORT DRIVER RESET TEST VDD VSS PA0
5 x 5 KEY SCANNER
C0 C1 C2 C3 C4
R0 R1 R2 R3 R4 KREQ
DISPLAY LINE COUNTER
Y ADDRESS REGISER
2/41
FEDL9090A-01
1 Semiconductor
ML9090A-01, -02
BLOCK DIAGRAM (2/2)
ML9090A-02
COM1 VIN VC1 VC2 VS1 VS2 DT COM18 SEG1 SEG80
VOLTAGE DOUBLER/ TRIPLER
18-OUT COMMON DRIVER
80-OUT SEGMENT DRIVER
SHIFT REGISTER V2 V3B V3A
Y ADDRESS DECODER Y ADDRESS COUNTER Y ADDRESS REGISER LCD BIAS VOLTAGE DIVIDING CIRCUIT
DATA LATCH
DISPLAY DATA RAM 80 x 18 BITS
INPUT OUTPUT INTERFACE
CONTROL REGISTER
CS CP DI/O
I/O BUFFER
X ADDRESS DECODER
X ADDRESS COUNTER
TIMING GENERATOR
X ADDRESS REGISTER
OSC1 OSC2
OSCILLATION CIRCUIT
1 PORT DRIVER RESET TEST VDD VSS PA0
5x5 KEY SCANNER
C0 C1 C2 C3 C4
R0 R1 R2 R3 R4 KREQ
DISPLAY LINE COUNTER
LINE ADDRESS DECODER
3/41
FEDL9090A-01
1 Semiconductor
ML9090A-01, -02
PIN CONFIGURATION (TOP VIEW) 1/2
ML9090A-01
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
103
SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA0
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
VDD OSC2 OSC1 DT V2 V3B V3A VIN VC1 VC2 VS1 VS2 VSS TEST RESET KREQ DI/O CS CP C0 C1 C2 C3 C4 R0 R1 R2 R3 R4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9
39
40
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SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10
128-pin plastic QFP
64
4/41
FEDL9090A-01
1 Semiconductor
ML9090A-01, -02
PIN CONFIGURATION (TOP VIEW) 2/2
ML9090A-02
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
103
SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 PA0
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
VDD OSC2 OSC1 DT V2 V3B V3A VIN VC1 VC2 VS1 VS2 VSS TEST RESET KREQ DI/O CS CP C0 C1 C2 C3 C4 R0 R1 R2 R3 R4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9
39
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SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10
128-pin plastic QFP
64
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FEDL9090A-01
1 Semiconductor
ML9090A-01, -02
FUNCTIONAL DESCRIPTIONS
Pin Functional Descriptions
Function Pin 85 CPU interface 84 86 87 100 Oscillation 101 OSC2 O Symbol CS CP DI/O KREQ OSC1 Type I I I/O O I Description Chip select signal input pin Shift clock signal input pin. This pin is connected to an internal Schmitt circuit Serial data signal I/O pin Key request signal output pin Connect external resistors. If using an external clock, input it from the OSC1 pin and leave the OSC2 pin open. Initial settings can be established by pulling the reset input to a "L" level. This pin is connected to an internal Schmitt circuit. Input pin for selecting the voltage doubler or voltage tripler. Test input pin. This pin is connected to the VSS pin. Input pins that detect status of key switches Key switch scan signal output pins Port A output Port B outputs (for ML9090A-01) Outputs for LCD segment drivers Outputs for LCD common drivers (for ML9090A-01) Outputs for LCD common drivers (for ML9090A-02) Logic power supply pin GND pin Voltage multiplier reference voltage power supply pin Capacitor connection pins for voltage multiplier Voltage multiplier output pin Voltage multiplier output pin LCD bias pins
88 Control signals 99 89 83 to 79 78 to 74 Port outputs 103 111 to 104 73 to 122 LCD driver outputs 121 to 112 121 to 104 102 90 95 Power supply 94, 93 92 91 98, 96, 97
RESET
I
DT TEST C0 to C4 R0 to R4 PA0 PB0 to PB7 SEG1 to SEG80 COM1 to COM10 COM1 to COM18 VDD VSS VIN VC1, VC2 VS1 VS2 V2, V3A, V3B
I I I O O O O O O -- -- -- -- -- -- --
Key scan signals
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FEDL9090A-01
1 Semiconductor
ML9090A-01, -02
Pin Functional Descriptions * CS Chip select input pin. An "L" level selects the chip, and an "H" level does not select the chip. During the "L" level, internal registers can be accessed. * CP Clock input pin for serial interface data I/O. An internal Schmitt circuit is connected to this pin. Data input to the DI/O pin is synchronized to the rising edge of the clock. Output from the DI/O pin is synchronized to the falling edge of the clock. * DI/O Serial interface data I/O pin. This pin is in the output state only during the interval beginning when key scan data read or RAM read commands are written until the CS signal rises. At all other times this pin is in the input state. (When reset, the input state is set.) In other words, this pin goes into the output state only when the key scan register or the display data RAM is read. The relation between data level of this pin and operation is listed below.
Data level "H" "L" LCD display Light ON Light OFF Port "H" "L" Key status ON OFF
* KREQ Key scan read READY signal output pin. Two scan cycles after a key switch is switched ON, this pin goes to an "H" level. When all key switches are OFF, this pin returns to an "L" level. This signal can be used as a flag. To use it as a flag, start the key-scan reading when the KREQ signal changes to an "H" level from an "L" level. If the key-scan reading starts when the KREQ signal changes to an "L" level from an "H" level, scanned data may be unstable. To avoid this, repeat the key-scan reading three times. When the key-scan reading starts when this pin goes to an "L" level, data when a key switch is off is read. * OSC1 Input pin for RC oscillation. An oscillation circuit is formed by connecting a resistor (R) of 56k 2% to this pin and the OSC2 pin. If an external master oscillation clock is to be input, input the master oscillation clock to this pin.
OSC1 R = 56 k (VDD = 2.7 to 5.5 V) R OSC2
* OSC2 Output pin for RC oscillation. An oscillation circuit is formed by connecting a resistor (R) of 56k 2% to this pin and the OSC1 pin. If an external master oscillation clock is to be input, leave this pin unconnected (open).
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FEDL9090A-01
1 Semiconductor
ML9090A-01, -02
* RESET Reset signal input pin. The initial state can be set by pulling this pin to an "L" level. Refer to the "Output, I/O and Register States in Response to Reset Input" page for the initial states of each register and display. An internal pull-up resistor is connected to this pin. An external capacitor is connected for power-on-reset operation. * TEST Test signal input pin. This pin is used for testing by Oki. Connect this pin to VSS. When a different connection is made, proper operation cannot be guaranteed. * R0 to R4 Key switch scan signal output pins. During the scan operation, "L" level signals are output in the order of R0, R1, ...R4. (Refer to the page entitled "Key scan" for details.) * C0 to C4 Input pins that detect the key switch status. Internal pull-up resistors are connected to these pins. Assemble a key matrix between these pins and the R0 to R4 pins. * PA0 General-purpose port A output pin. Because this pin can output a current of -15 mA, it is best suited as an LED driver. If this pin is used as an LED driver, insert an external current limiting resistor in series with the LED. If this pin is not used, leave it unconnected (open). * PB0 to PB7 General-purpose port B output pins. Each of the PB5 to PB7 pins has the same driving capability as the PA0 pin, namely the ability to output a current of -15 mA. These pins are only applicable to the ML9090A-01. Leave unused pins unconnected (open). * SEG1 to SEG80 Segment signal output pins for LCD driving. Leave unused pins unconnected (open). * COM1 to COM18 Common signal output pins for LCD driving. Leave unused pins unconnected (open). COM11 to COM18 are provided for the ML9090A-02 and PB0 to PB7 for the ML9090A-01. * VDD Logic power supply connection pin. * VSS Power supply GND connection pin. * DT This pin selects the voltage multiplier circuit. If this pin is connected to the VSS pin, the voltage doubler circuit is selected. If this pin is connected to the VDD pin, the voltage tripler circuit is selected. Do not change the value of the setting after power is turned on. * VC1, VC2 Capacitor connection pins for the voltage multiplier. Connect a 4.7 F capacitor between the VC1 and VC2 pins. If an electrolytic capacitor is used, connect the (+) side to pin VC2.
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FEDL9090A-01
1 Semiconductor
ML9090A-01, -02
* VS1 Voltage doubler voltage output pin. This pin outputs the doubled voltage that has been input to VIN. To increase stability of the power supply, connect a 4.7 F capacitor between this pin and VSS. When using the doubled voltage, connect this pin and VS2. * VS2 Voltage multiplier voltage output pin. Voltage multiplied by the factor specified by the DT pin setting is output from this pin. When the voltage tripler is used, to increase stability of the power supply, connect a 4.7 F capacitor between this pin and VSS. When using the voltage doubler, connect this pin and VS1. * VIN Voltage multiplier voltage input pin. The doubled or tripled voltage input to this pin is output from VS1 or VS2. * V2, V3A, V3B LCD bias pins for segment drivers. These pins are connected to internal bias dividing resistors. When using the ML9090A-01 (at 1/4 bias), connect V2 and V3A pins, and leave V3B unconnected (open). When using the ML9090A-02 (at 1/5 bias), connect V3A and V3B pins, and leave V2 unconnected (open).
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FEDL9090A-01
1 Semiconductor
ML9090A-01, -02
ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Bias Voltage Voltage Multiplier ReferenceVoltage Input Voltage Symbol VDD VBI VIN Condition Ta = 25C Ta = 25C Ta = 25C Ta = 25C *1 *2 Rating -0.3 to +7.0 -0.3 to +18.0 -0.3 to +9.0 -0.3 to +6.0 -0.3 to VDD +0.3 -20 -3 190 -55 to +150 Unit V V V Applicable Pins VDD VC1, VC2, VS1, VS2, V2,V3A, V3B VIN CS, CP, DI/O,OSC1, RESET, DT,TEST, C0 to C4 PA0, PB5 to PB7 PB0 to PB4 -- --
VI
Ta = 25C Ta = 25C Ta = 25C Ta = 85C --
V mA mA mW C
Output Current Power Dissipation Storage Temperature
IO PD Tstg
VSS is the reference voltage potential for all pins. *1: *2: When the voltage doubler is used. When the voltage tripler is used.
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Bias Voltage Voltage Multiplier ReferenceVoltage Operating Frequency Operating Temperature Symbol VDD VS2 VIN fop Top Condition -- -- *1 *2 R = 56k 2% -- Range 2.7 to 5.5 6.0 to 16.0 3.55 to 8.00 2.84 to 5.33 480 to 1200 -40 to +85 Unit V V V kHz C Applicable Pins VDD VS2 VIN OSC1 --
VSS is the reference voltage potential for all pins. *1: *2: When the voltage doubler is used. When the voltage tripler is used.
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FEDL9090A-01
1 Semiconductor
ML9090A-01, -02
ELECTRICAL CHARACTERISTICS
OSC Circuit Operating Conditions
Parameter Oscillation Resistance Symbol R Condition VDD = 2.7 V to 5.5 V Rating 56 *1 Unit k Applicable Pins OSC1, OSC2
*1:
Use a resistor with an accuracy of 2 %
OSC1 R OSC2
11/41
FEDL9090A-01
1 Semiconductor
ML9090A-01, -02
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD = 2.7 to 5.5 V, VS2 = 6 to 16 V, Ta = -40 to +85C)
Parameter "H" Input Voltage 1 "H" Input Voltage 2 "H" Input Voltage 3 "H" Input Voltage 4 "L" Input Voltage 1 "L" Input Voltage 2 "L" Input Voltage 3 "L" Input Voltage 4 "H" Input Current 1 "H" Input Current 2 "H" Input Current 3 "H" Input Current 4 "L" Input Current 1 "L" Input Current 2 "L" Input Current 3 "L" Input Current 4 "L" Input Current 5 "L" Input Current 6 "H" Output Voltage 1 "H" Output Voltage 2 "H" Output Voltage 3 "H" Output Voltage 4 "H" Output Voltage 5 "L" Output Voltage 1 "L" Output Voltage 2 "L" Output Voltage 3 "L" Output Voltage 4 Symbol VIH1 VIH2 VIH3 VIH4 VIL1 VIL2 VIL3 VIL4 IIH1 IIH2 IIH3 IIH4 IIL1 IIL2 IIL3 IIL4 IIL5 IIL6 VOH1 VOH2 VOH3 VOH4 VOH5 VOL1 VOL2 VOL3 VOL4 VOS0 Segment Output Voltage 1(1/4 bias) VOS1 VOS2 VOS3 Condition -- -- -- -- -- -- -- -- VI = VDD VI = VDD VI = VDD VI = VDD VDD = 5 V, VI = 0 V VDD = 5 V, VI = 0 V VI = 0 V VI = 0 V VDD = 3 V, VI = 0 V VDD = 3 V, VI = 0 V IO = -0.4 mA IO = -40 A IO = -15 mA IO = -2 mA IO = -50 A IO = 0.4 mA IO = 40 A IO = 1 mA IO = 1.8 mA IO = -10 A IO = 10 A IO = 10 A IO = +10 A Min. 0.85VDD 0.85VDD 0.85VDD 0.8VDD -- -- -- -- -- -- -- -- -0.02 -0.18 -- -- -4 -0.04 VDD - 0.4 0.9VDD VDD - 1.7 VDD - 1.2 VDD - 2.0 -- -- -- -- VS2 - 0.6 2/4VS2 - 0.6 2/4VS2 - 0.6 -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -0.05 -0.45 -- -- -10 -0.1 -- -- -- -- -- -- -- -- -- -- -- -- -- Max. -- -- -- -- 0.15VDD 0.15VDD 0.15VDD 0.2VDD 10 10 10 1 -0.1 -0.9 -10 -1 -25 -0.2 -- -- -- -- -- 0.4 0.1VDD 0.4 0.7 -- 2/4VS2 + 0.6 2/4VS2 + 0.6 VSS + 0.6 Unit V V V V V V V V A A A A mA mA A A A mA V V V V V V V V V V V V V SEG1 to SEG80 Applicable Pins OSC1 RESET CP CS, DI/O,C0 to C4 OSC1 RESET CP CS, DI/O,C0 to C4 RESET C0 to C4 DI/O OSC1, CS, CP,DT, TEST RESET C0 to C4 DI/O OSC1, CS, CP,DT, TEST RESET C0 to C4 DI/O, KREQ OSC2 PA0, PB5 to PB7 PB0 to PB4 R0 to R4 DI/O, KREQ OSC2 PA0, PB0 to PB7 R0 to R4
12/41
FEDL9090A-01
1 Semiconductor
ML9090A-01, -02
(VDD = 2.7 to 5.5 V, VS2 = 6 to 16 V, Ta = -40 to +85C) Parameter Common Output Voltage 1 (1/4 bias) Symbol VOC0 VOC1 VOC2 VOC3 VOS0 Segment Output Voltage 2 (1/5 bias) VOS1 VOS2 VOS3 VOC0 Common Output Voltage 2 (1/5 bias) VOC1 VOC2 VOC3 Condition IO = -10 A IO = 10 A IO = 10 A IO = +10 A IO = -10 A IO = 10 A IO = 10 A IO = +10 A IO = -10 A IO = 10 A IO = 10 A IO = +10 A External clock = 740 KHz Voltage Multiplier Voltage 1 VDB VIN = 3.55 to 8.0 V 1/4 bias *1 External clock = 740 KHz Voltage Multiplier Voltage 2 VTR VIN = 2.84 to 5.33 V 1/4 bias *2 Supply Current 1 Supply Current 2 Supply Current 3 LCD Driving Bias Resistance IDD1 IDD2 IVIN LBR R = 56K *3 External clock = 740 KHz *4 R = 56K *3 *5 -- -- -- 6.3 -- -- -- 9 0.95 0.7 2 13 mA mA mA k VDD VDD VIN VS2 - V2, V2 - V3B, V3A - VSS Min. VS2 - 0.3 3/4VS2 - 0.3 1/4VS2 - 0.3 -- VS2 - 0.6 3/5VS2 - 0.6 2/5VS2 - 0.6 -- VS2 - 0.3 4/5VS2 - 0.3 1/5VS2 - 0.3 -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- Max. -- 3/4VS2 + 0.3 1/4VS2 + 0.3 VSS + 0.3 -- 3/5VS2 + 0.6 2/5VS2 + 0.6 VSS+0.6 -- 4/5VS2 + 0.3 1/5VS2 + 0.3 VSS + 0.3 Unit V V V V V V V V V V V V COM1 to COM18 SEG1 to SEG80 COM1 to COM18 Applicable Pins
VIN x 1.83 -0.5
15 *6
VIN x 2
V
VS2
VIN x 2.46 -1.0
13 *7
VIN x 3
V
VS2
*1: *2: *3: *4: *6: *7:
Refer to Measuring Circuits 1 Refer to Measuring Circuits 2 Refer to Measuring Circuits 3 Refer to Measuring Circuits 4 VIN = 8 V, Ta = 25C VIN = 5.33 V, Ta = 25C
*5
LBR LBR
LBR
LBR LBR
VS2
V2
V3B
V3A
VSS
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FEDL9090A-01
1 Semiconductor
ML9090A-01, -02
Measuring Circuits
Measuring Circuit 1 Voltage multiplier voltage 1 When voltage doubler is used. 1/4 bias OPEN
VDD VIN
SEG1-SEG80 COM1-COM10
Measuring Circuit 2 Voltage multiplier voltage 2 When voltage tripler is used. 1/4 bias
VDD VIN
OPEN
VDDSEG1-SEG80 VIN VC1 VC2 VS1 VSS PAO VS2 OSC2 OSC1 TEST RESET f = 740 kHz OPEN OPEN
COM1-COM10
-
VDD VIN VC1 VC2 VS1 VS2 VSS PAO OSC2 OSC1 V2 OPEN OPEN VTR
V
4.7F 30% + 4.7F 30% +
4.7F - 30% + 4.7F 30%
+
VDB
V
4.7F30%
100A
+
100A
DT
OPEN
V3B V3A CS *1 CP COM11-COM18/ DI/O PB0-PB7 C0-C4
TEST RESET
f = 740 kHz
VDD
VDD
VDD
VDD
R0-R4
DT V2 OPEN V3B V3A CS *1 CP COM11-COM18/ DI/O PB0-PB7 C0-C4
VDD
R0-R4
OPEN
OPEN
IDD1
A
Measuring Circuit 3 Supply current 1 When voltage tripler is used
OPEN
VDD VIN VC1 VC2 VSS PAO OSC2 OSC1 OPEN
SEG1-SEG80 COM1-COM10
IDD2
A
Measuring Circuit 4 Supply current 2 When voltage tripler is used
OPEN
VDD
SEG1-SEG80 COM1-COM10
5.5 V IVIN
A
5.5 V 5.33 V - 4.7 F
5.33 V-
4.7F 30% +
4.7 F30% VS1 + 4.7 F30% VS2 + VDD OPEN
VC2 4.7 F30% VS1 + VS2
30% +
VIN VC1 VSS PAO OSC2 OSC1 TEST RESET *1
COM11-COM18/ PB0-PB7 C0-C4 R0-R4
OPEN OPEN
R = 56 k 4.7 F 30%+ 2%
VDD
DT TEST V2 V3B V3A RESET CS *1 CP COM11-COM18/ DI/O PB0-PB7 C0-C4 R0-R4
VDD
VDD DT OPEN V2 V3B V3A VDD CS CP DI/O
f = 740 kHz
VDD
OPEN
OPEN
*1:
PB0 - PB7 for ML9090A-01, and COM11 - COM18 for ML9090A-02
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FEDL9090A-01
1 Semiconductor
ML9090A-01, -02
Switching Characteristics
(VDD = 2.7 to 5.5 V, VS2 = 6 to 16 V, Ta = -40 to +85C) Parameter CP Clock Cycle Time CP "H" Pulse Width CP "L" Pulse Width CS "H" Pulse Width CP Clock Rise/fall Time CS Setup Time CS Hold Time DI/O Setup Time DI/O Hold Time DI/O Output Delay Time DI/O Output OFF Delay Time RESET Pulse Width External Clock Cycle Time External Clock "H" Pulse Width External Clock "L" Pulse Width External Clock Rise/fall Time Symbol tSYS tWH tWL tWCH tr, tf tCSU tCHD tDSU tDHD tDOD tDOFF tWRE tSES tWEH tWEL trE, tfE Condition -- -- -- -- -- -- -- -- -- CL = 50 pF CL = 50 pF -- -- -- -- -- Min 1000 400 400 200 -- 60 290 100 15 -- -- 2 833 316 316 -- Max -- -- -- -- 100 -- -- -- -- 200 200 -- -- -- -- 100 Unit ns ns ns ns ns ns ns ns ns ns ns s ns ns ns ns
Key Scan Characteristics
(VDD = 2.7 to 5.5 V, VS2 = 6 to 16 V, Ta = -40 to +85C) Parameter Symbol Register setting KT Key Scan Cycle Key Scan Invalid Time Tscn Tnop 0 1 0 1 1/3780 1/7560 1/4800 1/9600 Dividing ratio 7.9 15.8 10.0 20.0 Oscillation frequency 480 kHz 740 kHz 5.1 10.2 6.5 13.0 1200 kHz 3.1 6.2 4.0 8.0 ms Unit
Frame Frequency Characteristics
(VDD = 2.7 to 5.5 V, VS2 = 6 to 16 V, Ta = -40 to +85C) Model Parameter Symbol Display duty 1/8 ML9090A-01 Frame Frequency ML9090A-02 FRM 1/9 1/10 1/16 1/17 1/18 Dividing ratio 1/6144 1/6912 1/7680 1/6144 1/6528 1/6912 Oscillation frequency 480 kHz 78.1 69.4 62.5 78.1 73.5 69.4 740 kHz 120.4 107 96.3 120.4 113.3 107 1200 kHz 195.3 173.7 156.3 195.3 183.9 173.7 Hz Unit
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1 Semiconductor
ML9090A-01, -02
Clock synchronous serial interface timing diagrams Clock synchronous serial interface input timing
tWCH CS tCSU tSYS tr tWH tf CP tDSU DI/O tDHD - VIH4 - VIL4 tWL - VIH3 - VIL3 tCHD - VIH4 - VIL4
Clock synchronous serial interface input/output timing
tWCH CS tCSU tSYS tr tWH tf CP
1st Clock
- VIH4 - VIL4 tCHD
tWL
8th Clock 9th Clock
- VIH3 - VIL3 tDOFF VOH1 VOL1
tDSU DI/O VIH4 VIL4
tDHD VIH4 VIL4
tDOD VOH1 VOL1
Hiz
Reset timing
tWRE RESET - VIL2
External clock
trE tWEH tfE tWEL OSC1 tSES - VIH1 - VIL1
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ML9090A-01, -02
Key scan timing
Tscn Rn Tnop - VDD - VSS Key switch ON Scanning starts Key switch OFF Scanning stops Key switch ON Scanning starts
Frame frequency
- VS2 - V1 COM1 - V4 1/FRM - VSS 1/FRM
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Instruction Code List
Instruction code Descriptions D6 S4 D4 D4 -- Y4 -- -- -- -- Y3 Y2 Y1 Y0 X3 X2 X1 X0 D3 D2 D1 D0 D3 D2 D1 D0 S3 S2 S1 S0 D5 D4 D3 D2 D1 D0
Reads scan read count display bits (ST0 to ST2) and key scan data (S0 to S4) of the key scan register. Writes display data (D0 to D7) in the display data RAM after setting the X address or Y address. Reads display data (D0 to D7) from the display data RAM after setting the X address or Y address. Sets the X address (X0 to X3) of the display data RAM. Sets the Y address (Y0 to Y4) of the display data RAM.
Start byte
1 Semiconductor
Instruction
Fixed bit D7 D6 0 0 0 0 0 1 1 0 0 0 1 -- -- T4 T3 T2 T1 -- 0 0 INC WLS KT SHL -- -- 0 1 PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 to PTB7). 0 0 -- -- -- 1 1 -- -- -- 1 0 -- -- -- 0 1 D7 D6 D5 0 1 D7 D6 D5 0 0 ST2 ST1 ST0
RS R/W Register No. D7 D5 D4 D3 D2 D1 D0
Key scan register read
1
1
0
1
0
Display data RAM write
1
1
1
0
0
Display data RAM read
1
1
1
1
0
X address register set
1
1
0
0
0
Y address register set
1
1
0
0
0
Port register A set
1
1
0
0
0
PTA Controls the output of the general-purpose port A (PTA).
Controls the output of the general-purpose port B (PTB0
Port register B set
1
1
0
0
0
Control register 1 set
1
1
0
0
1
Sets the address increment X or Y direction (INC), display data word length (WLS), key scan time (KT), common DTY1 DTY0 driver shift direction (SHL), and display duty (DTY0, DTY1).
Control register 2 set
1
1
0
0
1
DISP Sets test mode (T1 to T4) and display ON/OFF (DISP).
: Word length select bit : Key scan cycle select bit : Display duty select bit
WLS KT DTY0, DTY1 SHL
RS R/W ST0 to ST2 S0 to S4 D0 to D7 X0 to X3 Y0 to Y4 PTA PTB0 to PTB7 INC
: Register select bit 1: RAM 0: Register : Read/write select bit 1: Read 0: Write : Key scan read count display bits : Key scan data : Write or read data of the display data RAM : X address of the display data RAM : Y address of the display data RAM : Port A data : Port B data (ML9090A-01 only) : Display data RAM address increment 1 : X direction, 0: Y direction
ML9090A-01, -02
FEDL9090A-01
DISP T1 to T4 --
1: 6 bits, 0: 8 bits 1: 10 ms, 0: 5 ms (1/8, 1/9, 1/10) (ML9090A-01) (1/16, 1/17, 1/18) (ML9090A-02) : Common driver shift direction select bit 1: COM10 COM1, 0: COM1 COM10 (ML9090A-01) 1: COM18 COM1, 0: COM1 COM18 (ML9090A-02) : Display ON/OFF select bit 1: Display ON, 0: Display OFF : Write "0" to use for test mode : Don't Care
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ML9090A-01, -02
Clock Synchronous Serial Transfer Example (WRITE)
Transfer start CS 1 CP 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Transfer complete
DI/O
"1" "1"
RS R/W D3
D2
D1
D0
D7
D6
D5
D4
D3
D2 D1
D0
Register bits Start byte
1st byte Instruction
Clock Synchronous Serial Continuous Data Transfer Example (WRITE)
Transfer start CS *1 1 CP 2 7 8 9 10 15 16 17 18 23 24 41 42 47 48 Transfer complete
DI/O
Start byte Instruction 1 Instruction 2 Instruction 5
*1:
Write data in 8 bits. If the CS signal falls when data input operation in 8 bits is not complete, the last 8-bit data write is invalid. (The previously written data is valid)
Clock Synchronous Serial Continuous Data Transfer Example (READ)
Transfer start CS *2 1 CP 2 8 9 10 11 15 16 17 18 23 24 41 42 47 48 Transfer complete
DI/O
Start byte
READ DATA1 READ DATA2
READ DATA5
Input state
Output state
*2:
A reading state appears only when the R/W bit is "1". The read data is valid only when the register is set to key scan read mode and display data read mode. Otherwise, the read data is invalid.
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FEDL9090A-01
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ML9090A-01, -02
Output pin, I/O Pin and Register States When Reset is Input Pin and register states while the RESET input is pulled to a "L" level are listed below.
Output pin, I/O pin DI/O KREQ OSC2 R0 to R4 PBA PB0 to PB7 (for ML9090A-01) SEG1 to SEG80 COM1 to COM10 (for ML9090A-01) COM1 to COM18 (for ML9090A-02) Input state "L" (VSS) Oscillating state "L" (VSS) High impedance High impedance "L" (VSS) "L" (VSS) "L" (VSS)
State
Register Key scan register Display data register X address register Y address register Port A register Port B register Control register 1 Control register 2 Reset to "0" Display data is retained Reset to "0" Reset to "0" Reset to "0" Reset to "0"
State
No change from value prior to reset input Display OFF
Power-On Reset The capacitance of an external capacitor that is connected to the RESET pin must be CRST [F] 12.5 x TR [s], where TR is rise time until power supply voltage to be supplied to the ML9090A-01/02 reaches 0.8 VDD (V) and CRST is the capacitance of an external capacitor connected to the RESET pin. (If TR = 10 [ms], CRST 0.125 [F]) The pulse width when an external reset signal is input should be more than TR. Set an instruction 10 s after the reset signal is released. Thereafter, this IC is accessible.
TR 0.9 VDD VDD 0.1 VDD Power supply voltage
0.85 VDD Accessible time RESET 10 s or more
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ML9090A-01, -02
Serial Interface Operation 1. Start byte A register that transfers instruction codes (including display data or key scan data) is selected by a content of the start byte (see below).
D7 "1" D6 "1" D5 RS D4 R/W D3 D2 D1 D0
Register number
(1) D7, D6 (fixed at "1") When selecting the start byte register, always write a "1" to bits D7 and D6. (2) D4 (R/W) (Read mode, Write mode select bit) 1: Read mode is selected 0: Write mode is selected (3) D5, D3 to D0 (Register number) The correspondence between each content of the start byte and each register or the display data RAM is listed in the table below.
D7 1 1 1 1 1 1 1 1
D6 1 1 1 1 1 1 1 1
D5 0 1 0 0 0 0 0 0
D4 1 1/0 0 0 0 0 0 0
D3 0 0 0 0 0 0 1 1
D2 0 0 0 0 1 1 0 0
D1 0 0 1 1 0 0 0 0
D0 0 1 0 1 0 1 0 1
Register name Key scan register Display data RAM X address register Y address register Port A register Port B register Control register1 Control register 2
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ML9090A-01, -02
Register Descriptions * Key scan register (KR)
D7 ST2 D6 ST1 D5 ST0 D4 S4 D3 S3 D2 S2 D1 S1 D0 S0
(1) D7 to D5 (ST2 to ST0) (Scan read counter) When reading 25-bit key scan data, these bits indicate the number of times scan data has been read. Every time key scan data is read, these bits (ST2 to ST0) are automatically incremented over the range of "000" to "100". After counting to "100", this key scan data read counter is reset to "000". If the RESET pin is pulled to a "L" level, these bits are reset to "0". (2) D4 to D0 (S4 to S0) (Key scan read data bits) These bits are read as 25-bit serial data that expresses the key switch status (1 = ON, 0 = OFF). Data is divided into 5 groups and read. (For the read order, refer to the description below.) The read count is indicated by bits ST2 to ST0. S4 to S0 key scan data corresponds to each SWN0 of the key matrix shown in figure 1. The relation between the key scan data, key matrix signal and each SWN0 of the key matrix is shown below. If the RESET pin is pulled to a "L" level, these bits are reset to "0".
ST2 0 0 0 0 1
ST1 0 0 1 1 0
ST0 0 1 0 1 0
S4 SW04 SW14 SW24 SW34 SW44
S3 SW03 SW13 SW23 SW33 SW43
S2 SW02 SW12 SW22 SW32 SW42
S1 SW01 SW11 SW21 SW31 SW41
S0 SW00 SW10 SW20 SW30 SW40 R0 R1 R2 R3 R4
(Note)
SW00 to SW44 swithes are shown in Figure1.
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ML9090A-01, -02
ML9090A-01, -02
C0 C1 C2 C3 C4
R0 SW00 SW01 SW02 SW03 SW04
R1
SW10
SW11
SW12
SW13
SW14
R2
SW20
SW21
SW22
SW23
SW24 R3
SW30
SW31
SW32
SW33
SW34
R4
SW40
SW41
SW42
SW43
SW44
Figure 1
(Note)
To recognize simultaneous depression of three or more key switches, add a diode in series to each key.
Cm
Rn
Rn + 1
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ML9090A-01, -02
Key Scan The key scanning starts when a key switch is pressed on and ends after all key switches are detected to be off. The KREQ signal changes from the low level "L" to the high level "H" two cycles after key scanning started. This signal can be used as a flag. To use it as a flag, start key-scan reading when the KREQ signal changes from "L" to "H". In some cases, scanned data may be unstable if key scan reading starts when the level of the KREQ signal changes from "H" to "L". To avoid this, repeat the key-scan reading three times. All key switch inputs are inhibited for about 1.26 cycle after all key switches are detected to be off while the KREQ signal is at the "H" level. The KREQ signal is reset when all key switches are detected to be off or when a low-level signal is applied to the RESET pin.
R0 R1 R2 R3 R4 Key switch ON Scanning starts KREQ Key data reading starts. Key switch input is invalid. Key switch OFF Scanning stops. Key switch ON Scanning starts.
Note 1:
When three or more key switches are pressed at the same time, the ML9090A-01/02 may recognize that an unpressed key switch is pressed. Therefore, to recognize simultaneous depression of three or more key switches, add a diode in series to each key. (See Figure 1.) To ignore simultaneous depression of three or more key switches, a program may be required to ignore all key data which contain three or more consecutive "1" values.
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ML9090A-01, -02
* Display data RAM (DRAM)
D7 -- D6 D5 D4 8-bit DATA 6-bit DATA D3 D2 D1 D0
The display data register writes and reads display data to and from the liquid crystal display RAM. The contents of this register are written to or read from the address set by the X address register and Y address register. The bit length of display data can be selected by the WLS bit of control register 1. If 6-bit data has been selected, writing to D7 and D6 is invalid, and if read, their values will always be "0". D7 is the MSB (D5 in the case of 6-bit data) and D0 is the LSB. The X address and Y address should be set immediately before writing or reading display data. However, only one-time settings of X address and Y address are required immediately before successive writings or readings. Either X address or Y address may be set first. Even if the RESET pin is pulled to a "L" level, the contents of this register will not change. * X address register (XAD)
D7 D6 -- D5 D4 D3 D2 XAD D1 D0
The X address register sets the X address for the liquid crystal display RAM. The address setting range is 0 to 9 (00H to 09H) when 8-bit data is selected by the WLS bit. This register starts counting up from the set value each time RAM is read or written. When the register count returns to 0 from the maximum value 9, the Y address is automatically incremented. Thereafter, the Y address is counted in a loop fashion from 0 to 9. The address setting range is 0 to 13 when 6-bit data is selected. This register starts counting up from the set value. When the register count returns to 0 from 13, theY address is automatically incremented. Thereafter, the Y address loops from 0 to 13. Proper operation is not guaranteed if values outside this range are set. Writing to bits D7 through D4 is invalid. If the RESET pin is pulled to a "L" level, these bits are reset to "0". * Y address register (YAD)
D7 D6 -- -- D5 D4 D3 D2 YAD (ML9090A-02) D1 D0
YAD (ML9090A-01)
The YAD register sets a Y address of RAM for the liquid crystal display. The Y address setting range varies according to the setting of the DTY bits (bits D1 and D0) of the control register 1 (to be described later). This register starts counting up from the set value each time RAM is read or weitten. When the register count returns to 0 from the maximum value (7 to 17), the X address is also incremented automatically. The Y address is counted in a loop fashion as shown below.
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FEDL9090A-01
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ML9090A-01, -02
Model ML9090A-01
Duty 1/8 1/9 1/10 1/16
Y register setting range and loop range 0 to 7 (00H to 07H) 0 to 8 (00H to 08H) 0 to 9 (00H to 09H) 0 to 15 (00H to 0FH) 0 to 16 (00H to 10H) 0 to 17 (00H to 11H)
Invalid addres setting range 8 to 15 (08H to FH) 9 to 15 (09H to FH) 10 to 15 (AH to FH) 16 to 31 (10H to 1FH) 17 to 31 (11H to 1FH) 18 to 31 (12H to 1FH)
ML9090A-02
1/17 1/18
When an invalid Y address is set, counting of invalid Y addresses varies according to the selected duty although its operation is not assured. In case the duty is 1/8 or 1/16, the register counts up to a maximum invalid Y address value (15 for the ML9090A-01 or 31 for the ML9090A-02) and back to 0. At the same time, the X address is also incremented. In case the duty is 1/9 or 1/17, the register counts back to 0 at address "Y address setting plus 1" after an invalid Y address is set. At the same time, the X address is also incremented. In case the duty is 1/10 or 1/18, the register counts back to 0 at address "Y address setting plus 1" and at address "Y address setting plus 1" after an invalid Y address is set. At the same time, the X address is also incremented. After this, the Y address count loops in a range corresponding to the selected duty. Both read and write operations on bits D7 to D4 of the ML9090A-01 are invalid. Both read and write operations on bits D7 to D5 of the ML9090A-02 are invalid. This register is reset to "0" when the RESET pin is made low. * Port register A (PTA)
D7 D6 D5 D4 -- D3 D2 D1 D0 PTA
The port register A sets (to "1") and resets (to "0") general-purpose port A data. The setting of the PTA bit (D0 bit) corresponds to the PA0 output pin. If the RESET pin is pulled to a "L" level, this register is reset to "0" and the PA0 pin goes to high impedance. After the RESET pin is pulled to a "H" level, if port data is set in this register, the PA0 pin is released from its high impedance state and outputs the corresponding port data. * Port register B (PTB)
D7 PTB7 D6 PTB6 D5 PTB5 D4 PTB4 D3 PTB3 D2 PTB2 D1 PTB1 D0 PTB0
The port register sets (to "1") and resets (to "0") general-purpose port B data. The settings of the PTB0 to PTB7 bits (D0 to D7 bits) correspond to the PTB0 to PTB7 output pins. If the RESET pin is pulled to a "L" level, this register is reset to "0" and pins PTB0 through PTB7 go to high impedance. After the RESET pin is pulled to a "H" level, if port data is set in this register, pins PTB0 through PTB7 are released from their high impedance states and output the corresponding port data.
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* Control register 1 (FCR1)
D7 INC D6 WLS D5 KT D4 SHL D3 -- D2 -- D1 DTY1 D0 DTY0
(1) D7 (INC) Address increment direction 1: X direction address increment 0: Y direction address increment This bit sets the address increment direction of the display RAM. The display RAM address is automatically incremented by 1 every time data is written to the display data register. Writing a "1" to this bit sets "X address increment", and writing a "0" sets "Y address increment". For further details regarding address incrementing, refer to the page entitled "X, Y Address Counter Auto Increment", Even if the RESET pin is pulled to a "L" level, the value of this bit will not change. (2) D6 (WLS) (Word Length Select) 1: 6-bit word length select 0: 8-bit word length select This bit selects the word length of data to be written to and read from the display RAM. If "1" is written to this bit, data will be read from and written to the display RAM in 6-bit units. If "0" is written to this bit, data will be read from and written to the display RAM in 8-bit units. Even if the RESET pin is pulled to a "L" level, the value of this bit will not change. (3) D5 (KT) (Key scan time) Key scan time select bit 1: 10 ms 0: 5 ms This bit selects the key scan cycle time. In the case of a 740 kHz oscillating frequency, writing a "1" to this bit sets the key scan cycle time at 10 ms, writing a "0" sets the key scan cycle time at 5 ms. Even if the RESET pin is pulled to a "L" level, the value of this bit will not change. (4) D4 (SHL) (Common driver shift direction select bit) This bit selects the shift direction of common drivers. The relationship between this bit and shift directions are shown below. Even if the RESET Pin is set to "L", this bit remains unchanged.
Model SHL 1 ML9090A-01 0 Duty 1/8 1/9 1/10 1/8 1/9 1/10 1/16 1 ML9090A-02 0 1/17 1/18 1/16 1/17 1/18 Shift direction COM8 COM9 COM10 COM1 COM1 COM1 COM16 COM17 COM18 COM1 COM1 COM1 COM1 COM1 COM1 COM8 COM9 COM10 COM1 COM1 COM1 COM16 COM17 COM18
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(5) D1, D0 (DTY1, DTY0) (Display duty select bit) This bit selects the display duty. The correspondence between each bit and display duty is shown in the chart below. Even if the RESET pin is pulled to a "L" Level, the values of these bits will not change.
Model
Code 0 1 2 3 0 1 2 3
DTY1 0 0 1 1 0 0 1 1
DTY0 0 1 0 1 0 1 0 1
Display duty 1/8 1/9 1/10 1/10 1/16 1/17 1/18 1/18
ML9090A-01
ML9090A-02
* Control register 2 (FCR2)
D7 -- D6 D5 T4 D4 T3 D3 T2 D2 T1 D1 -- D0 DISP
(1) D2 to D5 (T1 to T4) (Test mode select bit) These bits are used to test the IC. "0" must be written to these bits. (2) D0 (DISP) (Display ON/OFF mode bit) 1: Display ON mode 0: Display OFF mode This bit selects whether the display is ON or OFF. Writing a "1" to this bit selects the display ON mode. Writing a "0" to this bit selects the display OFF mode. At this time, the COM and SEG pins will be at the VSS level. Even if this bit is set to "0", the display RAM contents will not change. If the RESET pin is pulled to a "L" level, this register is reset to "0".
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ML9090A-01, -02
Display Screen and Memory Address Allocation The ML9090A-01/02 contains display data RAM (80 bits by 18 bits) of a bitmap type. The allocation of memory addresses varies according to the selected word length (6 bits or 8 bits) as shown in Figure 2: 0 to 9 for selection of 8 bits per word or 0 to 13 for selection of 6 bits per word. The X address 13 in the 6-bits/word mode has two display memory bits. The two bits (D5 and D4) starting from bit D5 of the display data register are written in memory and the other bits (D3 to D0) are ignored.
Address Allocation in the 8-bits/word mode
(X address) (Y address) 0 0 1 (D7) (D0) (8 bits) 17 1 2 9
Address Allocation in the 6-bits/word mode
(X address) (Y address) 0 0 1 (D5) (D0) (6 bits) 17 (D5) (D4) (2 bits) 1 2 13
Figure 2 Display Memory Addresses
In the 8-bits/word mode, data to be displayed is written in display memory with the D7 data of the display data register at address (Xn, Yn) and the D0 data at address (Xn + 7, Yn). Similarly, In the 6-bits/word mode, data to be displayed is written in display memory with the D5 data of the display data register at address (Xn, Yn) and the D0 data at address (Xn + 5, Yn). See Figure 3. Data "1" in display memory represents turning on the corresponding display segment and data "0" in display memory represents turning off the corresponding display segment.
Segment output
(SEG1)
(SEG2)
(SEG3)
(SEG4)
(SEG5)
(SEG6)
(SEG7)
X address
(SEG8)
Common output (COM1) (COM2) Y0 Y1
X address
1
0
1
0
1
0
1
0
(D7) (D5)
(D0) For 8 bits per word (D0) For 6 bits per word
(COM18)
Y17
RAM for 80 dots by 18 dots display
Figure 3 Display Screen Bit Allocation and Memory Addresses
X79
1
X0
X1
X2
X3
X4
X5
X6
X7
(SEG80)
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X*Y address Counter Auto Increment The liquid crystal display RAM for the ML9090A-01/02 has an X-address counter and a Y-address counter. Each address counter has an Auto Increment function. When display data is read or written, this function increments either of these X- and Y-address counters (which is selected by the INC bit (D7 bit) of the control register 1). INC bit = "0" selects the Y-address counter. INC bit = "1" selects the X-address counter. The address counting cycle of the X address counter varies according to the selected word length (8 bits or 6 bits) : X address range of 0 to 9 in the 8-bits/word mode or X address range of 0 to 13 in the 6-bits/word mode. When the X address count returns to 0 from a maximum value (9 in the 8-bits/word mode or 13 in the 6-bits/word mode), the Y address is also incremented automatically. The relationship between display duties and Y address count ranges is shown below. When the Y-address counter returns to 0 from a maximum value, the X address is also incremented automatically.
Model ML9090A-01
Duty 1/8 1/9 1/10 1/16
Y-address count range (cycle) 0 to 7 0 to 8 0 to 9 0 to 5 0 to 16 0 to 17
Maximum Y address count 7 8 9 15 16 17
ML9090A-02
1/17 1/18
Note:
If an invalid address (outside the address count range) is given to the X- or Y- address counter, its counting will not be assured.
Example of incrementing the X-address (8 bits per word and 1/18 duty)
Example of incrementing the Y-address (8 bits per word and 1/18 duty)
0 X address 1 9
0 0
1
X address 2
9 Y address
0 1 2
Y address
1
17 17
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FEDL9090A-01
1 Semiconductor
ML9090A-01, -02
Liquid Crystal Driving Waveform Example (1) 1/8 duty (1/4 bias) (ML9090A-01)
Common line No.
81
2
34
5
6
7
8
12
3
4
5
67
8
1
2
3
VS2 V1 C0M1 V2, V3A, V3B V4 VSS VS2 V1 C0M2 V2, V3A, V3B V4 VSS VS2 V1 C0M8 V2, V3A, V3B V4 VSS
A non-selectable waveform is output from COM9 and COM10 outputs.
Common line No.
81
23
4
5
6
78
1
23
4
56
7
81
23 VS2 V1
V2, V3A, V3B SEGn V4 VSS
: Light ON : Light OFF
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FEDL9090A-01
1 Semiconductor
ML9090A-01, -02
Liquid Crystal Driving Waveform Example (2) 1/9 duty (1/4 bias) (ML9090A-01)
Common line No.
9
12
345
6
78
9
12
3
45
6
78
9
1 VS2 V1
C0M1
V2, V3A, V3B V4 VSS VS2 V1
C0M2
V2, V3A, V3B V4 VSS VS2 V1
C0M9
V2, V3A, V3B V4 VSS
A non-selectable waveform is output from the COM10 output.
912 3 45 678 9 12 3 45 6 78 9 1 VS2 V1 SEGn V2, V3A, V3B V4 VSS
Common line No.
: Light ON : Light OFF
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FEDL9090A-01
1 Semiconductor
ML9090A-01, -02
Liquid Crystal Driving Waveform Example (3) 1/10 duty (1/4 bias) (ML9090A-01)
Common line No.
10 1
2
3
4
56
7
8 9 10 1 2
3
4
567
8 9 10
VS2 V1 C0M1 V2, V3A, V3B V4 VSS VS2 V1 C0M2 V2, V3A, V3B V4 VSS VS2 V1 C0M10 V2, V3A, V3B V4 VSS
10 1
2
3
45
6
78
9 10 1
2
34
5
67
8
9 10
Common line No.
VS2 V1 V2, V3A, V3B SEGn V4 VSS
: Light ON : Light OFF
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FEDL9090A-01
1 Semiconductor
ML9090A-01, -02
Liquid Crystal Driving Waveform Example (4) 1/16 duty (1/5 bias) (ML9090A-02)
15 16 1 2 3 4 5 6 7 8 9 10 11 12 1314 1516 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5
Common line No.
VS2 V1 C0M1 V2 V3A, V3B V4 VSS VS2 V1 C0M2 V2 V3A, V3B V4 VSS VS2 V1 C0M16 V2 V3A, V3B V4 VSS
A non-selectable waveform is output from COM17 and COM18 outputs.
15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 1011 12 13 14 15 16 1 2 3 4 5
Common line No.
VS2 V1 SEGn V2 V3A, V3B V4 VSS : Light ON : Light OFF
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FEDL9090A-01
1 Semiconductor
ML9090A-01, -02
Liquid Crystal Driving Waveform Example (5) 1/17 duty (1/5 bias) (ML9090A-02)
16 17 1 2 3 4 5 6 7 8 9 10 1112 13 14 15 16 17 1 2 3 4 5 6 7 8 9 1011 1213 14 1516 17 1 2 3 4 5
Common line No.
VS2 V1 C0M1 V2 V3A, V3B V4 VSS VS2 V1 V2 V3A, V3B V4 VSS VS2 C0M17 V1 V2 V3A, V3B V4 VSS
C0M2
A non-selectable waveform is output form the COM18 output.
16 17 1 2 3 4 5 6 7 8 9 10 1112 13 14 15 16 17 1 2 3 4 5 6 7 8 9 1011 12 13 14 15 16 17 1 2 3 4 5
Common line No.
VS2 V1 SEGn V2 V3A, V3B V4 VSS : Light ON : Light OFF
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*Please view this page at 150% magnification.
FEDL9090A-01
1 Semiconductor
ML9090A-01, -02
Liquid Crystal Driving Waveform Example (6) 1/18 duty (1/5 bias) (ML9090A-02)
Common line No.
1718 1 2 3 4 5 6 7 8 9 101112131415161718 1 2 3 4 5 6 7 8 9 101112131415161718 1 2 3 4 5
C0M1
VS2 V1 V2 V3A, V3B V4 VSS VS2 V1 V2 V3A, V3B V4 VSS VS2 V1 V2 V3A, V3B V4 VSS
C0M2
C0M18
17 18 1 2 3 4 5 6 7 8 9 1011121314 15161718 1 2 3 4 5 6 7 8 9 101112131415161718 1 2 3 4 5
Common line No.
SEGn
VS2 V1 V2 V3A, V3B V4 VSS : Light ON : Light OFF
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FEDL9090A-01
1 Semiconductor
ML9090A-01, -02
Power-On Flowchart
Start VDD turned on VIN turned on Reset signal is input Control register 1 setting External reset or power-on reset INC, WLS, KT, SHL, DTY1, DTY0 settings
Display Data RAM settings
Port register A, port register B, display data RAM settings according to specifications.
No
Is input of initial screen data complete ? Yes
Set DISP of control register 2 to "1" Start displaying initial screen Setting complete
Power-Off Flowchart
LCD driving state VIN turned off VDD turned off
[Cautions] * When the power supply is ON or OFF, the following power supply sequence should be used. At the time of power supply ON: Logic power supply ON multiplied reference supply voltage (VIN) ON At the time of power supply OFF: Multiplied reference supply voltage (VIN) OFF logic power supply OFF or both OFF * The lines between output pins, and between output pins and other pins (input pins, I/O pins or power supply pins), should not be short circuited.
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FEDL9090A-01
1 Semiconductor
ML9090A-01, -02
APPLICATION CIRCUIT
Application Example 1 (1/10 duty, 1/4 bias, voltage doubler)
LCD panel 80 x 10 dots graphic
VCC
Temperature compensating and stabilizing circuits
COM1-COM10 4.7 F + VIN VC1 VC2 VS1
SEG1-SEG80 VDD
VDD = 5 V
DT VSS PA0
+ 4.7 F
VS2 OSC1
ML9090A-01
V2 OPEN V3B V3A CPU CS CP
PORT OR SERIAL PORT
56 k OSC2 TEST RESET R4 R3 R2 R1 R0
1 F
DI/O KREQ PB0-PB7 C0 C1 C2 C3 C4
General-purpose ports
5x5 Key Matrix
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FEDL9090A-01
1 Semiconductor
ML9090A-01, -02
Application Example 2 (1/18 duty, 1/5 bias, voltage tripler)
LCD panel
80 x 18 dots graphic
VCC
Temperature compensating and stabilizing circuits
COM1-COM18 4.7 F + VIN VC1 VC2 VS1
SEG1-SEG80 VDD DT VSS PA0
VDD = 5 V
4.7 F 4.7 F
+
+
VS2 OSC1
OPEN
ML9090A-02
V2 V3B V3A OSC2 TEST RESET R4 R3 R2 R1 C0 C1 C2 C3 C4 R0
56 k
CPU CS CP
PORT OR SERIAL PORT
1 F
DI/O KREQ
5x5 Key Matrix
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FEDL9090A-01
1 Semiconductor
ML9090A-01, -02
PACKAGE DIMENSIONS
(Unit: mm)
QFP128-P-1420-0.50-K
Mirror finish
5
Notes for Mounting the Surface Mount Type Package
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5m) 1.19 TYP. 4/Nov. 28, 1996
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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FEDL9090A-01
1 Semiconductor
ML9090A-01, -02
NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2001 Oki Electric Industry Co., Ltd.
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